Traditionally, all active die on an integrated circuit (IC) wafer have been electrically tested. Usually, when the die are tested, a wafer map is created that contains information on the X-Y coordinates of the wafer, referenced to a potentially good first die. The wafer map generally also stores bin information that indicates whether a given die is good or bad. The wafer map is then used at each subsequent wafer process step. Unfortunately, if a first wafer process step or any subsequent wafer process step utilizes the wrong first die, the wafer map is inaccurate, potentially resulting in bad die being classified as good die and good die being classified as bad die.
What is needed is a first die indicator for an integrated circuit wafer that allows first die integrity to be maintained throughout various wafer processing steps.